Authentic | True |
Event | Digital System Design and Verification |
Name | Anupriya Shinde |
Organization | Vidyalankar Institute of Technology (VIT) |
Date | July 1-8, 2024 |
Coordinator | Prof. Siddharth Tallur |
Dean | Prof. Siddhartha Ghosh |
Course Content
- Comprehensive lectures on CPLD/ FPGA Technology and structural, behavioral modeling and FSM implementation in HDL
- Tutorials on familiarity with Krypton CPLD board, Quartus-II simulation and synthesis tool
- Concepts on generalized test bench for digital logic simulation, scan chain based testing and verification of digital logic implemented on the CPLD board
- Structural and behavioral modeling of combinational and sequential digital circuits, implementation, and verification of the design in HDL
- Design, implementation, and verification of Finite State Machines (FSMs) using structural and behavioral modeling in HDL
- Simple application building using the concepts learned through the topics covered